[LTP] tst_atomic_add_return() implementation for sparc

[Cyril Hrubis]

Hi!
> I'm trying to add tst_atomic_add_return() implementation for sparc.
> It seems to me from current kernel sources [1], that it uses atomic_add_return() from
> <linux/atomic.h> [2] (generated by __atomic_op_fence()).
> But it's out of my scope to generate the correct implementation.
> Anyone having a clue how to implement it?

If you look a bit deeper the __atomic_op_fence() does:

#define __atomic_op_fence(op, args...)					\
({									\
	typeof(op##_relaxed(args)) __ret;				\
	smp_mb__before_atomic();					\
	__ret = op##_relaxed(args);					\
	smp_mb__after_atomic();						\
	__ret;								\
})
#endif

And the smp_bm_*() macros are translated just to barrier() in case of sparc in
arch/sparc/include/asm/barrier_64.h which is defined in
include/linux/compiler-gcc.h:

	#define barrier() __asm__ __volatile__("": : :"memory")

Then the atomic_add_return_relaxed() translates to atomic_add_return() which is defined in include/asm-generic/atomic.h and translates to:


        raw_local_irq_save(flags);                                      \
        ret = (v->counter = v->counter + i);                            \
        raw_local_irq_restore(flags);                                   \
                                                                        \


So something as:

	int ret;
	__asm__ __volatile__("": : :"memory");
	ret = (counter = counter + 1);
        __asm__ __volatile__("": : :"memory");
	return ret;

Should work, but I do not have any sparc hardware for testing...

-- 
Cyril Hrubis
chrubis@suse.cz