[LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79)

[Petr Vorel]

Hi Hui,

> AndesCore CPU test fails due to an illegal instruction at the first
> jumpfunc(), caused by executing incorrect instructions after
> self-modifying code.

> On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
> ensuring that subsequent instruction fetch on a RISC-V hart will see
> any previous data stores already visible to the same RISC-V hart.

> Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
> In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
> each hart to flush their local i-caches.

Reviewed-by: Petr Vorel <pvorel@suse.cz>

BTW what "#79" in the git message subject means?

Kind regards,
Petr