[LTP] [PATCH] hugemmap15: Add support for loongarch

[wangxuewen]

From: wangxuewen <wangxuewen@kylinos.cn>

Before this patch:
./hugemmap15
tst_test.c:1137: TCONF: Signal handler for this architecture hasn't been written
After this patch：
./hugemmap15
tst_hugepage.c:84: TINFO: 3 hugepage(s) reserved
tst_tmpdir.c:316: TINFO: Using /tmp/LTP_hug7F2RcZ as tmpdir (tmpfs filesystem)
tst_test.c:1097: TINFO: Mounting none to /tmp/LTP_hug7F2RcZ/hugetlbfs fstyp=hugetlbfs flags=0
tst_test.c:1900: TINFO: LTP version: 20250130-164-gae2792765
tst_test.c:1904: TINFO: Tested kernel: 6.6.0-27.0.v2503.ky11.loongarch64 #1 SMP Mon Mar 10 13:32:48 UTC 2025 loongarch64
tst_kconfig.c:88: TINFO: Parsing kernel config '/proc/config.gz'
tst_test.c:1722: TINFO: Overall timeout per run is 0h 00m 30s
hugemmap15.c:104: TINFO: SIGILL at 0x7fffedffff80 (sig_expected=0x7fffedffff80)
hugemmap15.c:104: TINFO: SIGILL at 0x7fffe9ffff80 (sig_expected=0x7fffe9ffff80)
hugemmap15.c:104: TINFO: SIGILL at 0x7fffe5ffff80 (sig_expected=0x7fffe5ffff80)
hugemmap15.c:104: TINFO: SIGILL at 0x7fffe1ffff80 (sig_expected=0x7fffe1ffff80)
......
hugemmap15.c:104: TINFO: SIGILL at 0x7ffef1ffff80 (sig_expected=0x7ffef1ffff80)
hugemmap15.c:104: TINFO: SIGILL at 0x7ffef1ffff80 (sig_expected=0x7ffef1ffff80)
hugemmap15.c:221: TPASS: Successfully tested dcache to icache flush

Summary:
passed   1
failed   0
broken   0
skipped  0
warnings 0

Signed-off-by: wangxuewen <wangxuewen@kylinos.cn>
---
 testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
index f9fd22694..1dde9e87b 100644
--- a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
+++ b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
@@ -27,7 +27,7 @@
 #if defined(__powerpc__) || defined(__powerpc64__) || defined(__ia64__) || \
 	defined(__s390__) || defined(__s390x__) || defined(__sparc__) || \
 	defined(__aarch64__) || (defined(__riscv) && __riscv_xlen == 64) || \
-	defined(__i386__) || defined(__x86_64__) || defined(__arm__)
+	defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__loongarch__)
 
 #include <setjmp.h>
 
@@ -45,7 +45,7 @@ static void cacheflush(void *p)
 {
 #if defined(__powerpc__)
 	asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
-#elif defined(__arm__) || defined(__aarch64__) || defined(__riscv)
+#elif defined(__arm__) || defined(__aarch64__) || defined(__riscv) || defined(__loongarch__)
 	__clear_cache(p, p + COPY_SIZE);
 #else
 	(void)p;
@@ -68,7 +68,6 @@ static void jumpfunc(int copy, void *p)
 		memcpy(p, l, COPY_SIZE);
 		cacheflush(p);
 	}
-
 	goto *p;
  dummy:
 	tst_res(TWARN, "unreachable?");
@@ -96,6 +95,14 @@ static void sig_handler(int signum, siginfo_t *si, void *uc)
 			siglongjmp(sig_escape, SUCC_JMP);
 		siglongjmp(sig_escape, FAIL_JMP + SIGILL);
 	}
+#elif defined(__loongarch__)
+	if (signum == SIGILL) {
+		void *pc = (void *)((ucontext_t *)uc)->uc_mcontext.__pc;
+		tst_res(TINFO, "SIGILL at %p (sig_expected=%p)", pc, sig_expected);
+		if (pc == sig_expected)
+			siglongjmp(sig_escape, SUCC_JMP);
+		siglongjmp(sig_escape, FAIL_JMP + SIGILL);
+	}
 #elif defined(__i386__) || defined(__x86_64__) || defined(__arm__)
 	/* On x86, zero bytes form a valid instruction:
 	 *	add %al,(%eax)		(i386)
-- 
2.25.1