[LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Kubaj, Piotr]

2026-03-16 (月) の 12:55 +0000 に Andrea Cervesato さんは書きました:
> Hi!
> 
> > Verify for all online logical CPUs that their highest performance
> > value are
> > the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> > ---
> >  testcases/kernel/power_management/.gitignore  |  1 +
> >  .../power_management/high_freq_hwp_cap_cppc.c | 57
> > +++++++++++++++++++
> >  2 files changed, 58 insertions(+)
> >  create mode 100644
> > testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > 
> > diff --git a/testcases/kernel/power_management/.gitignore
> > b/testcases/kernel/power_management/.gitignore
> > index 0c2a3ed4b..c13bca1c4 100644
> > --- a/testcases/kernel/power_management/.gitignore
> > +++ b/testcases/kernel/power_management/.gitignore
> > @@ -1 +1,2 @@
> > +high_freq_hwp_cap_cppc
> >  pm_get_sched_values
> > diff --git
> > a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > new file mode 100644
> > index 000000000..4cbb81f0b
> > --- /dev/null
> > +++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +/*
> > + * Copyright (C) 2025-2026 Intel - http://www.intel.com/
> > + */
> 
> Remove space
Do you mean that double space? Removed. Other than that, I couldn't
find any redundant space.

> > +
> > +/*\
> > + * Verify for all online logical CPUs  that their highest
> > performance value are
> 
> Double space before "that"
> 
> > + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> > + */
> > +
> > +#include "tst_test.h"
> > +
> > +static int nproc;
> > +
> > +static void setup(void)
> > +{
> > +	nproc = tst_ncpus();
> > +}
> > +
> > +static void run(void)
> > +{
> > +	for (int i = 0; i < nproc; i++) {
> > +		char path[PATH_MAX];
> > +		unsigned long long msr_highest_perf = 0,
> > sysfs_highest_perf = 0;
> > +
> > +		snprintf(path, PATH_MAX,
> > "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
> 
> snprintf(path, sizeof(path), ..) is better.
Done.

> 
> > +		SAFE_FILE_SCANF(path, "%llu",
> > &sysfs_highest_perf);
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > sysfs_highest_perf);
> > +
> > +		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
> > +		int fd = SAFE_OPEN(path, O_RDONLY);
> > +
> > +		if (pread(fd, &msr_highest_perf,
> > sizeof(msr_highest_perf), 0x771) < 0) {
> > +			SAFE_CLOSE(fd);
> > +			tst_brk(TBROK | TERRNO, "MSR read error");
> > +		}
> 
> Simply use SAFE_PREAD(). fd will be closed when test ends.
Done.

> 
> > +		SAFE_CLOSE(fd);
> > +		msr_highest_perf &= (1ULL << 8) - 1;
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > msr_highest_perf);
> > +
> > +		if (msr_highest_perf != sysfs_highest_perf)
> > +			tst_brk(TFAIL, "CPU %d: highest
> > performance values differ between sysfs and MSR", i);
> 
> Why tst_brk() ? It's supposed to be tst_res(TFAIL, ..).
I actually find tst_brk() cleaner, because it ends the test when
there's a failure which removes the need for a check later, but I
changed it according to your suggestion.

> 
> > +	}
> > +
> > +	tst_res(TPASS, "Test pass");
> > +}
> > +
> > +static struct tst_test test = {
> > +	.needs_kconfigs = (const char *const []) {
> > +		"CONFIG_X86_MSR",
> 
> The CPPC sysfs interface also requires CONFIG_ACPI_CPPC_LIB to be
> built.
Right, added.

> 
> > +		NULL
> > +	},
> > +	.needs_root = 1,
> > +	.setup = setup,
> > +	.test_all = run
> > +};
> > -- 
> > 2.47.3
> > 
> > -------------------------------------------------------------------
> > --
> > Intel Technology Poland sp. z o.o.
> > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc |
> > VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 |
> > NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
> > Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w
> > rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu
> > nadmiernym opoznieniom w transakcjach handlowych.
> > 
> > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego
> > adresata i moze zawierac informacje poufne. W razie przypadkowego
> > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz
> > trwale jej usuniecie; jakiekolwiek przegladanie lub
> > rozpowszechnianie jest zabronione.
> > This e-mail and any attachments may contain confidential material
> > for the sole use of the intended recipient(s). If you are not the
> > intended recipient, please contact the sender and delete all
> > copies; any review or distribution by others is strictly
> > prohibited.
> > 
> > 
> > -- 
> > Mailing list info: https://lists.linux.it/listinfo/ltp
> 
> There's also no runtest entry for this test, so it can't be run in
> the testing
> suites by kirk.
> 
> Kind regards,
> --
> Andrea Cervesato
> SUSE QE Automation Engineer Linux
> andrea.cervesato@suse.com
---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.